1. Field of the Invention
The present invention relates to semiconductor memories, and particularly to architecture and organization of a random-access memory array having lower power consumption read operations.
2. Description of Related Art
Semiconductor random-access memory devices or sub-systems using arrays of dynamic memory cells (e.g., 1-transistor/1-capacitor (1T/1C) cells) have consistently provided greater density and lower cost per bit than those using static memory cells (e.g., 6-transistor (6T) cells, or 4-transistor/2-resistor (4T/2R) cells). However, such dynamic random-access memory arrays have historically also been lower in performance when compared to static random-access memory arrays. Consequently, system designers have typically chosen dynamic memory arrays (e.g., commercially available dynamic random access memories, or DRAMs) when high density and low cost are required, such as for CPU main memory applications. Conversely, designers have typically chosen static memory arrays when the highest possible performance is required, such as for cache memory and high speed buffer applications. Examples of static memory array devices or sub-systems include commercially available static random access memories (SRAMs) and CPU-resident on-board cache memory sub-systems.
The reasons often cited for the lower performance of dynamic memory arrays include the destructive sensing of all memory cells common to the addressed word line (encountered in virtually all dynamic memory arrays) and the consequential need to restore data back into each sensed memory cell during the active cycle, the need to equilibrate bit lines and various other differential nodes and to precharge various circuit nodes between active cycles, and the requirement for periodic refreshing of all dynamic memory cells.
The need for ever-increasing memory performance at reasonable cost continues unabated. It is being driven by numerous advances toward higher frequency and higher speed applications. For example, the increasing bandwidth demands of computer networking and the internet, the increasing speeds of commercially available processors, and the proliferation of high-frequency wireless communication systems are all driving the need for higher performance memory subsystems.
In addition to the increased speed requirements of memory systems, there is also an increasing need for memory with reduced power consumption. Many prior art memories have a data bus that is one word wide coupled to a memory array. Such circuits perform a read cycle each time a read request occurs. Other prior art memories have a data bus that is two data words wide coupled to a memory array. In a read cycle, the memory retrieves both data words and outputs a first data word (the requested data word) in response to the read request. If the second data word is requested in the next read cycle, then the second data word is presented in response to the second read request with no activity required of the memory array. Otherwise, the second data word is discarded. Many memory devices are utilized in environments that require low power usage (e.g. portable computing systems). Therefore, there is an unfilled need for memory devices with low power consumption characteristics.